Electronic devices such as Field Programmable Gate Arrays (FPGAs) typically require some form of address generation, especially in high bandwidth applications such as Digital Signal Processing (DSP), communications, or networking. This is typically done using Configurable/Complex Logic Block (CLB) resources in the FPGA to implement sequence generators, comparators and other associated logic required to produce the necessary control signals. For memory intensive operations, the addresses and accompanying control signals are often routed through the FPGA fabric.
The general trend in the FPGA field is to either absorb functionality that is external to the FPGA into the FPGA itself, or use hard (non-programmable) logic for commonly used circuits as for example when using dedicated multipliers in a FPGA design.
Address generator circuits are generally realized in hardware using counters or Linear Feedback Shift Registers (LFSRs) to produce the necessary addressing sequence. Comparators are then coupled with the sequence generators and are used to detect various conditions such as full, almost full, empty, etc. This combination of components can fulfill the addressing requirements for a variety of vector operations, including First-In First-Out (FIFOs), stacks, line buffering and Multiply-and-Accumulate Finite Impulse Response (MAC FIR) filtering.
Address generator circuits implemented in hard logic alone however cannot be reused for more than one of the above applications, since once implemented; the circuit cannot be modified. If an address generator is designed in hard logic (hard wired) to support the addressing needs of a FIFO for example, it cannot provide the addressing needs for a MAC FIR filter in most instances. A need thus exists in the art for an address generator that can alleviate some of the above-mentioned problems.